Solid-state imaging devices include multiple pixel portions arranged one- or two-dimensionally in a photodetecting section, each pixel portion being provided with a photoelectric converting element. Photodiodes are commonly used as photoelectric converting elements. In photodiodes having a normal pn-junction structure, charges generated due to incidence of light are accumulated in a junction capacitor. For this reason, when a certain bias voltage is applied to a general photodiode and then shut off for incidence of light, the capacitance of the junction capacitor fluctuates depending on the amount of accumulated charge, resulting in a fluctuation in the output voltage. That is, in the relationship: Q (accumulated charge amount)=C (junction capacitance)×V (output voltage) that is known to be true, since the junction capacitance C varies depending on the change in the accumulated charge amount Q, the output voltage V does not become linear to the accumulated charge amount.
There have been known such buried photodiodes as those disclosed in Patent Document 1 that are capable of solving the problem above. In exemplary buried photodiodes, an n−-type second semiconductor region is formed on a p-type first semiconductor region and a p+-type third semiconductor region is formed on the second semiconductor region and the periphery thereof, and pn-junctions are formed between the first and second semiconductor regions as well as the second and third semiconductor regions. In such buried photodiodes, the second semiconductor region can be depleted completely so that the junction capacitance does not depend on the voltage and that the junction capacitance is reduced, whereby the output voltage becomes linear to the accumulated charge amount. Thus, charges generated in the pn-junctions can be readout almost completely, and since the depletion layer cannot come into contact with the interface between the semiconductor region and an insulating film region that is generally provided on the semiconductor region, the generation of leak current at the interface between the semiconductor region and the insulating film region is suppressed, resulting in an improved S/N ratio and/or linearity for light detection.
Patent Document 1: Japanese Published Unexamined Patent Application No. 11-274454